1. Field of the Invention
The present invention relates to programmable memory devices, particularly one-time programmable (OTP) devices, for use in memory arrays.
2. Description of the Related Art
A One-Time Programmable (OTP) device, such as electrical fuse, is a device that can be programmed only once. The programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state (depending on either fuse or anti-fuse).
An electrical fuse is a common OTP element that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, or other transition metals. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon or metal gate, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The electrical fuse can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
A conventional OTP memory cell 10 is shown in FIG. 1. The cell 10 consists of an OTP element 11 and an NMOS program selector 12. The OTP element 11 is coupled to the drain of the NMOS 12 at one end, and to a high voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a low voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the OTP cell 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common OTP elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The resistive cell 10 can be organized as a two-dimensional array with all Sel's and V−'s in a row coupled as wordlines (WLs) and a ground line, respectively, and all V+'s in a column coupled as bitlines (BLs).
Another conventional OTP memory cell 15 is shown in FIG. 2. The OTP memory cell has an OTP element 16 and a diode 17 as program selector. The OTP element 16 is coupled between an anode of the diode 17 and a high voltage V+. A cathode of the diode 17 is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the OTP element 16 can be programmed into high or low resistance states, depending on voltage/current and duration. The diode 17 can be a junction diode constructed from a P+ active region on N well and an N+ active region on the same N well as the P and N terminals of a diode, respectively. In another embodiment, the diode 17 can be a diode constructed from a polysilicon structure with two ends implanted by P+ and N+, respectively. The P or N terminal of either junction diode or polysilicon diode can be implanted by the same source or drain implant in CMOS devices. Either the junction diode or polysilicon diode can be built in standard CMOS processes without any additional masks or process steps. The OTP cells 15 can be organized as a two-dimensional array with all V+'s in the same columns coupled together as bitlines (BLs) and all V−'s in the same rows coupled together as wordline bars (WLBs).
The program current of an OTP memory, especially for fuse memory, can be easily larger than 10 mA for CMOS generation above 40 nm and the program time can be easily longer than 10 us. If an OTP memory has 256 Kb, the total program time can be up to 2.56 seconds, which is unacceptably long in today's manufacturing. Long tester time results in higher costs. Normally, testing a chip requires only about 2-3 sec. maximum. If programming an OTP memory requires more than 1 sec, the cost of a chip using OTP would be too high.
In the past, programming a fuse memory is one bit at a time. This is partly because of high programming current incurred such that programming multiple bits at the same time would need very wide power and/or ground buses to handle high current. For example, if programming a bit requires 10 mA, programming 8 bits concurrently would require 80 mA. Even a 5 ohm resistance in the power or ground buses would have voltage drop of 400 mV. This is unacceptable high, especially the supply voltage has been reduced over the years from 5 Volts (V), to 3.3 V, even to about 1.2 V. Thus, there is a need for improved techniques and designs for concurrently programming bits of an OTP memory, such as fuse memory.